New PDF release: Defect and Fault Tolerance in VLSI Systems: Volume 1

By Israel Koren

This e-book comprises an edited choice of papers offered on the overseas Workshop on illness and Fault Tolerance in VLSI platforms held October 6-7, 1988 in Springfield, Massachusetts. Our thank you visit all of the participants and particularly the individuals of this system committee for the tricky and time-consuming paintings all in favour of settling on the papers that have been offered within the workshop and reviewing the papers integrated during this e-book. thank you also are because of the IEEE computing device Society (in specific, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the collage of Massachusetts at Amherst for sponsoring the workshop, and to the nationwide technological know-how beginning for assisting (under supply quantity MIP-8803418) the keynote handle and the distribution of this ebook to all workshop attendees. the target of the workshop used to be to convey t. ogether researchers and practition­ ers from either and academia within the box of illness tolerance and yield en­ ha. ncement in VLSI to debate their mutual pursuits in defect-tolerant architectures and versions for built-in circuit defects, faults, and yield. development during this quarter used to be bogged down by means of the proprietary nature of yield-related facts, and by way of the shortcoming of applicable boards for disseminating such info. The target of this workshop was once hence to supply a discussion board for a discussion and alternate of perspectives. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. okay. Jain from the college of South Florida as basic co-chairmen, is being organized.

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From eq. (9), the yield of a chip of area A can be estimated from the observed yield of a chip of area A o, (A > Ao), with (11) using eq. (10) to infer the value of J(Ao) from the observed yield Y(Ao). It should be borne in mind that no matter what model is used, the yield of a new product, usually of larger area, is necessarily estimated from the known yield of existing product by area scaling the inferred average number of faults per chip of the known product. As eq. (7) and eq. (11) both show, 1(A) is scaled to the inferred value of J(Ao) by the area ratio (A/Ao).

29 (I), pp. 87-97 (1985). 18. W. Maly, "Modeling of Lithography Related Yield Losses for CAD ofVLSI Circuits", Trans. Computer-Aided Design, vol. CAD-4 (3), pp. 166-177 (1985). 19. W. Maly and J. Deszcka, "Yield Estimation Model for VLSI Artwork Evaluation", Electronics Letters, vol. 19 (6), pp. 226-227 (1983). 20. A. V. 0556 (1981 ). 21. A. V. 0562 (1982). 22. A. V. Ferris-Prabhu, "Computation of the Critical Area in Semiconductor Yield Theory", Proc. European Conference on Electronic Design Automation, (Univ.

The detection probability of a fault is really a conditional probability. It is the probability of detection by an input vector, given the fact that the fault is present. We have studied this probability in a recent paper [7]. In the present work, we also consider the fault occurrence probability. It is defined for each fault as the probability of its being found on a chip. Just as all faults are not equally detectable, they also do not occur with equal probability. The product 47 of these two probabilities is the absolute failure probability of a chip by a test vector.

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